EventOnline

Virtual: Shift-Left Performance Engineering for Agentic AI with CI/CD

SEP23
09:00

About this event

Speaker: Kandasamy Selvaraj | LinkedIn

Topic: Shift-Left Performance Engineering for Agentic AI with CI/CD Performance Signatures

Agenda:
πŸ•› 9:00–9:05 β€” Welcome
πŸ•› 9:05–9:55 β€” Kandasamy Selvaraj | LinkedIn \- Shift\-Left Performance Engineering for Agentic AI with CI/CD Performance Signatures
πŸ•› 9:55–10:00 β€” Closing
Summary:
Summary :
Years ago, I built automated performance gates into CI/CD pipelines that cut production defects by 80% and sped up deployments by 40%. The idea was simple. Catch a problem in the pipeline, where it's cheap to fix, instead of waiting for production to find it for you. That discipline is now standard in traditional software. It barely exists yet in agentic AI.

Response time, error rate, and throughput have been the standard SLO dimensions for as long as most of us have been doing this. They're necessary for an agentic pipeline, but they're not sufficient. An agent can meet every one of those three and still be a problem: it took six tool calls and three LLM calls to get a simple answer, a supervising agent delegated a task to a subagent that never properly completed it, one agent in a chain timed out while the overall request still returned something, or it pushed average token usage per trace well past what the system was designed to handle. None of that shows up in a response time chart. All of it shows up in the trace.

This talk is about treating trace data as the source for a new generation of SLOs built specifically for agentic pipelines part of shift left performance gate. I'll walk through what these new dimensions look like in practice: tool call count and LLM call count per trace, chain depth, tool failure and retry rate, delegation errors between agents, agent-level timeouts, and average tokens per trace. I'll cover a concrete starting point I use, flagging any trace that exceeds five tool calls or two LLM calls as a real gate condition, using trace data from a Langfuse integration wired directly into the performance gate rath

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